The present application relates to a transistor using an oxide semiconductor, a method of manufacturing the transistor, a semiconductor unit, a method of manufacturing the semiconductor unit, and to a display and an electronic apparatus which are provided with the transistor.
In recent years, along with increase in size and definition of a display, a thin film transistor (TFT) of a drive device is also demanded to have a high mobility, and a TFT using an oxide semiconductor such as oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), aluminum (Al), or titanium (Ti), or an oxide of a mixture thereof has been developed. In particular, a TFT using a composite oxide of Zn, In, and Ga has a high electron mobility and exhibits excellent electrical characteristics as compared with a TFT using amorphous silicon (a-Si:H) typically used in a liquid crystal display and the like.
In the above-described active drive liquid crystal display or organic electroluminescence (EL) display, the TFT is used as a drive device, and charge corresponding to a signal voltage for writing image is retained by a retention capacity. However, if a parasitic capacity generated in a cross region between the gate electrode and the source-drain electrode of the TFT is increased, variation of the signal voltage occurs, which may result in deterioration of image quality.
In the organic EL display in particular, there is a possibility that manufacturing yield is lowered in association with the issue in the parasitic capacity. Therefore, some attempts for decreasing the parasitic capacity has been made (for example, Japanese Unexamined Patent Application Publication Nos. 2011-228622, 2012-015436, and 2007-220817, “Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors”, J. Park, et al., Applied Physics Letters, American Institute of Physics, 2008, Vol. 93, 053501, and “Improved Amorphous In—Ga—Zn—O TFTs”, R. Hayashi, et al., SID 08 DIGEST, 2008, 42.1, pp. 621-624). In Japanese Unexamined Patent Application Publication Nos. 2011-228622, 2012-015436, and 2007-220817, and “Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors”, J. Park, et al., Applied Physics Letters, American Institute of Physics, 2008, Vol. 93, 053501, there is described a top gate TFT formed by a method in which a gate electrode and a gate insulating film are provided on the same position of a channel region of an oxide semiconductor film in a planar view, and then a region exposed from the gate electrode and the gate insulating film of the oxide semiconductor film is decreased in resistance to form source-drain regions, namely, a so-called self alignment. On the other hand, in “Improved Amorphous In—Ga—Zn—O TFTs”, R. Hayashi, et al., SID 08 DIGEST, 2008, 42.1, pp. 621-624, a bottom gate TFT having self alignment structure is disclosed.